The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to control systems for a chemical mechanical polishing apparatus.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, it is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a “standard” or a fixed-abrasive pad. A standard polishing pad has durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles, if a standard pad is used, is supplied to the surface of the polishing pad.
Problems in CMP is overpolishing (the removal of too much material from the substrate) and underpolishing (the removal of too little material from the substrate) of the substrate. Both underpolishing and overpolishing reduce the substrate yield.
A conventional control method 500 for making the wafer layer thickness match a desired thickness is illustrated in FIG. 5. Initially, a preset polishing time is selected for qualifying wafers that should result in nominal underpolishing (step 502). Several qualifying wafers, e.g., one to four wafers, are polished for this preset polishing time (step 504) and then cleaned and dried (step 506). The qualifying wafers are then transferred to a stand-alone thickness metrology device that measures the thickness of the one or more layers of the substrate (step 508). Steps 502–508 typically take about one-half to two hours. Based on the thickness measurements, the operator of the polishing apparatus manually adjusts the polishing time so that the resulting layer thickness should match the desired target thickness (step 510).
When device wafers are to be polished, they are polished by lot using the adjusted polishing time (512), cleaned and dried (step 514), and transferred by lot to the stand-alone thickness metrology device for measurement of the layer thickness of one or more of the wafers (step 516). If the device wafers are underpolished, they are reworked by sending them back to the polishing apparatus for additional polishing (step 518), and the polishing time is again manually adjusted (step 510), e.g., increased, so that the resulting layer thickness more closely matches the desired target thickness. On the other hand, if the device wafers are overpolished, they must be scrapped (step 520), and the polishing time is again manually adjusted, e.g., decreased, so that the resulting layer thickness more closely matches the desired target thickness. Once the device wafers have been polished, any underpolished qualification wafers are repolished (step 522).
Unfortunately, this conventional process has several problems. There is significant potential for miscalculation of the polishing time, and when the polishing time is incorrect, and entire lot of substrates is misprocessed. The frequency of monitoring is low, so that if the process parameters drift, resulting in a drift in the polishing rate, the polishing apparatus is unable to compensate. In addition, manual calculation of the polishing time is operator intensive and prone to error, and there is extensive non-productive time while the polishing apparatus idles after the qualifying wafers have been processed.